1. [Field of the Invention]
The present invention relates to a memory device, and particularly relates to a memory device which needs precharging of a bit line.
2. [Description of the Related Art]
FIG. 14 is a circuit diagram of DRAM (dynamic random access memory) according to Japanese Patent Application Laid-open No. Hei 8-263983. As a cause of occurrence of a standby current in DRAM, there is a DC (direct current) due to cross failure between a word line WL and a bit line BL. Specifically, when there is an insulation failure between the word line WL and the bit line BL, the voltage of the bit line BL decreases, so that a standby current increases. In order to reduce this, a current limiting element Q20 is arranged between precharge circuits Q13, Q14, Q15 on the bit line BL and a precharge power supply 1401 so as to limit a precharge power supply current supplied to the location where the cross failure occurs.
The arrangement of the current limiting element Q20 between the precharge circuits Q13, Q14, Q15 on the bit line BL and the precharge power supply 1401 enables to limit a direct current originated in the cross failure in a standby state. On the other hand, at the time of precharging bit lines BL, bBL, a precharge current which can be supplied to the bit lines BL, bBL is similarly limited, so that an operation of equalizing the voltage of the bit lines BL, bBL with a desired bit line precharge voltage becomes slow. Particularly, in the case where a bit line precharge voltage which becomes a reference voltage when reading data is set lower than the intermediate potential between a logical value 1 and a logical value 0 of a memory cell so as to improve an overall data holding characteristic, a direct short level between the complementary bit lines BL and bBL and a bit line precharge voltage becomes different, and if the operation of equalizing the bit line voltage with the precharge voltage is slow, the reference voltage does not return to desired level until the next reading. Consequently, the effect of improving the data holding characteristic becomes small, and an AC (alternating current) in a standby state increases.
As described above, the current value of the current limiting element Q20 cannot be set equal to or smaller than a current value which cannot satisfy precharging characteristics of the bit lines BL, bBL. Accordingly, the increase in standby current is large when the number of cross failures increases, so that a yield of the standby current with respect to the standard deteriorates.
FIG. 15A and FIG. 15B are a circuit diagram and a signal waveform diagram of DRAM according to Japanese Patent Application Laid-open No. 2000-182374. Regarding the above-described problem, this patent application discloses an elemental technology for improving a precharge characteristic.
A bit line precharge/equalize circuit 15 is shared by memory cell arrays on both sides respectively of a shared sense amplifier, a current limiting element Q20 and a switching transistor Q30 are arranged in parallel between the precharge/equalize circuit 15 and a line 40 of precharge voltage Vbleq, and further a control circuit 30 is included which turns on the switching transistor Q30 for a predetermined period by receiving a control signal from a precharge/equalize circuit 15. In the case that bit lines BLR, bBLR of the memory cell array on the other side of the shared sense amplifier become floating and the level thereof decreases while the memory cell array on one side of the shared sense amplifier is being accessed, the switching transistor Q30 is turned on for a predetermined period at the time of precharging to thereby raise the bit line level to the precharge voltage level.
In the above-described Japanese Patent Application Laid-open No. 2000-182374, when returning the levels of the bit lines BLR, bBLR changed during a floating period to a predetermined level at the time of precharging, the precharge voltage Vbleq is supplied to the bit lines BL, bBL by the switching transistor Q30, and while being in a standby state, a precharge voltage is supplied by the depletion-type current control elements Q20 arranged in parallel. Thus, two types of elements Q20 and Q30 are arranged in parallel for two operations, and therefore the area of elements in the sense amplifier increases accordingly.
Furthermore, in the case that an accessing period to the adjacent memory cell array becomes long and a floating period of the bit line becomes long, a shift of the bit line voltage from the precharge voltage becomes large, and the time to return it to a predetermined voltage by precharging becomes long. However, in the case that a precharge time of refreshing operation is included in a critical path for accessing as in pseudo-SRAM (static random access memory), an access time becomes slow.